The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Operational amplifiers are often used in signal processing applications, such as filter circuits, amplifier circuits, driver circuits, etc. Referring now to FIGS. 1A-1C, a class-A output stage with an NMOS driver, a class-A output stage with a PMOS driver, and a class-AB output stage are shown, respectively.
The first class-A output stage of FIG. 1A includes an NMOS transistor 10 that has a gate 12, a drain 14, and a source 16. The gate 12 is connected to an input terminal 18 that is supplied with an input signal voltage vi and a DC bias voltage VbiasN. The drain 14 is connected to a first current source 20, which is in turn connected to a voltage supply terminal 22 having potential VDD. The source 16 is connected to ground 24. A first load resistance RL1 is coupled between the drain 14 and an analog ground terminal 26 having a voltage potential that is one half of the voltage supply VDD or VDD/2. Voltage output of the transistor 10 is taken from the drain 14 at an output terminal 28 across the load resistance RL1. The potential of the output terminal 28 is vo+VDD/2, where vo is the output signal voltage.
The second class-A output stage of FIG. 1B includes a PMOS transistor 30 having a gate 32, a source 34, and a drain 36. The second gate 32 is connected to an input terminal 38 that is supplied with the input signal voltage vi and the DC bias voltage VbiasP. The source 34 is connected to a voltage supply terminal 40. The drain 36 is connected to a second current source 42, which is in turn connected to ground 44. A second load resistance RL2 is coupled between the drain 36 and an analog ground terminal 48. Voltage output of the transistor 30 is taken from the drain 36 at an output terminal 49 across the load resistance RL2. The potential of the output terminal 49 is vo+VDD/2.
The class-AB output stage of FIG. 1C includes a PMOS transistor 50 and an NMOS transistor 52. The PMOS transistor 50 has a gate 54, a source 56, and a drain 58. The NMOS transistor 52 has a gate 60, a source 62, and a drain 64. The gate 54 is supplied with the input signal voltage vi and the DC bias voltage VbiasP. The gate 60 is supplied with the input signal voltage vi and the DC bias voltage VbiasN. The drains 58 and 64 are connected directly to each other via an output terminal 66. The source 56 is connected to a voltage supply terminal 68. The source 62 is connected to ground 70. A third load resistance RL3 is connected between the output terminal 66 and an analog ground terminal 72. The potential of the output terminal 66 is vo+VDD/2.
The quiescent current IQ for the above output stages is defined as the current through each of the output stages in absence of input and output AC signals vi and vo. The quiescent current IQ for the class-A drivers of FIGS. 1A and 1B is determined solely by the current IR of the current sources 20 and 42 such that the quiescent current IQ is equal to the current IR. The DC bias voltages VbiasN and VbiasP are automatically adjusted such that the NMOS and PMOS transistors carry the current IR when the negative feedback loops (not shown) across the amplifiers are closed.
The class-AB output stage provides improved performance over the class-A output stages. The first class-A output stage can sink, but cannot source more than the quiescent current IQ into the load resistance RL1. The second class-A output stage can source, but cannot sink more than the quiescent current IQ into the load resistance RL2. Although the class-AB output stage is capable of sinking and sourcing more than the quiescent current IQ, the class-AB output stage has other associated disadvantages and limitations, some of which are described below.
The class-AB output stage is also more efficient than the class-A output stages, as the quiescent current IQ value associated with the class-AB stage can be considerably smaller than that of the class-A output stages. However, the quiescent current IQ for the class-AB output stage cannot be easily determined. The DC bias voltages VbiasN and VbiasP have to be adjusted to the correct values so that the quiescent current IQ is precisely determined. Also, this adjustment cannot be done by simply closing the negative feedback loop of the operational amplifier, as the loop does not contain information for determining the appropriate quiescent current IQ value required. Therefore, when the negative feedback loop is closed the quiescent current IQ may be set to any arbitrary value. As such, to provide the appropriate quiescent current IQ, the design of a class-AB output stage is more complicated compared to that of a class-A output stage.
In general, there are two methods that are used in the design of a class-AB output stage with deterministic values of the quiescent current IQ. The first method includes the use of an additional feedback loop which senses the quiescent current IQ, compares it against a reference current IR and corrects the bias voltages VbiasN and VbiasP such that the quiescent current IQ is equal to a positive constant k multiplied by the reference current IR. This approach introduces increased complexity and often leads to a three-stage amplifier, which is difficult to design.
The second method includes determining the bias voltages VbiasN and VbiasP of the class-AB output stage separately using two separate translinear loops. The first loop is used to set a first quiescent current IQ of the PMOS transistor to kIR. The second loop is used to set a second quiescent current IQ of the NMOS transistor also to kIR. A disadvantage of this method is that mismatches occur in the set quiescent current IQ values for the NMOS and PMOS transistors, since they are determined by two different circuits. The mismatched values result in increased input reference offset voltage for the amplifier. Thus, although the second method is simpler than the first, it suffers from higher input offset voltages and to changes in the quiescent current IQ values with process, temperature and power supply voltage variations. Also, the second method is not suitable for lower power supply voltages because of the higher voltage of operation required by the translinear loops.
In addition, both of the class-AB methods described above are high speed application limited. The loops that maintain the quiescent current IQ, for both of the methods, are limited in their ability to track fast changing signals. For this reason, a disturbance in the amplifier exists due to the bias voltage VbiasN being greater and/or the bias voltage VbiasP being less than normal. The disturbance remains until the loops have settled properly. This results in a high shunt current IsH that flows from the voltage supply terminal to ground for the period of the disturbance. The current IsH may be significantly greater than the quiescent current IQ, thus reducing efficiency.